Seminar: Network on Chip Architectural Level Power Consumption of Network on Chip

Network on chip is an emerging research topic nowadays in SoC (System on Chip) design. To fulfill the high-speed communication between different parts on a chip like microprocessor, memory or DSP etc., the people must develop new method and algorithm for fast interconnection between these components. At the same time, the power consumption of a chip especially from the interconnects of the chip becomes more and more important for the whole power optimization. With the high speed and great amount of data exchange among the chip components, power problem must be solved in novel methodology and adaptive structure of NoC (Network on Chip). This report topic concentrates on the power consumption at architectural level of NoC. First, some basic interconnect architectures will be introduced, for example, global interconnect networks. And then, some power issues of these architectures are introduced in general, like clustering. And next, the main discussion is focusing on the power consumption of switching and routing by employing specific algorithm. Finally, an example, MAIA chip, which uses reconfigurable heterogeneous chip architecture, is presented.